1. Field of the Invention
This invention relates to the field of interrupt processing. In particular, the invention is related to interrupt processing on a parallel bus.
2. Description of Related Art
Fundamental to the performance of any computer system, a processor performs a number of operations including controlling various intermittent "services" requested by peripheral devices coupled to the computer system. These services may include data transmission, data capture or any other data manipulative operations essential to the functionality of the peripheral devices. One type of interrupt delivery mechanisms, namely an Advanced Programmable Interrupt Controller ("APIC") interrupt delivery mechanism, is currently being used to detect an interrupt request from one of the peripheral devices and to advise the processor that a particular service corresponding to the interrupt request needs to be performed.
Referring to FIG. 1, an illustrative diagram of the conventional APIC interrupt delivery mechanism typically implemented within a computer is shown. The interrupt delivery mechanism distributes interrupt requests via an APIC bus 10 from an I/O APIC 20 coupled to a peripheral device (not shown) to a "local" APIC (not shown) of a host processor 30. Typically, the APIC bus 10 is a two-bit serial bus supporting the transmission of a Programmable Interrupt Controller Data ("PICD[1:0]#") signal having a bit representation in accordance with well-established APIC protocol. The PICD[1:0]# signal is a bi-directional serial message passing on the APIC bus 10 to transfer interrupt information such as interrupt type, arbitration data, interrupt vector, checksum, and status. As further shown, a Programmable Interrupt Controller Clock ("PICCL") signal is used as an input clock to the host processor 30 for synchronous operation of APIC bus 10.
While the APIC interrupt delivery mechanism is functional, it possesses a number of drawbacks. One drawback is that the APIC interrupt delivery mechanism relies on a slow, serial transmission rate, a maximum operation frequency of approximately 16.67 megahertz ("MHz"). Since interrupt processing is usually time critical, the slow serial transmission rate may have an impact on the host processor's ability to respond to critical events, especially real-time events. Another drawback is that the I/O APIC device has to be electrically compatible with the host processor both in physical and performance characteristics. As the host processor becomes faster, I/O APIC device may not respond accordingly.
Yet another drawback is that the conventional APIC interrupt delivery mechanism relies on a complicated communication protocol. If the peripheral device wishes to send additional information to a host memory, such information is initially sent to a buffer queue located within a chipset of the computer. However, before sending the interrupt via the PICD[1:0]# signal to the host processor, the I/O APIC device has to instruct the chipset to "flush" the buffer queue. The I/O APIC device 20 and the chipset usually have to go through a handshaking protocol to ensure that the additional information related to the interrupt is properly transferred to the main memory.
Thus, briefly stated, there are two disadvantages associated with the prior interrupt delivery mechanism. The first disadvantage is slow processing due to (i) low-bandwidth of the APIC bus supporting transmission of only a limited number of bits at a time and (ii) a handshaking protocol between the I/O APIC device and the chipset. The second disadvantage is that the interrupt delivery mechanism is not scalable, precluding one from taking advantage of increased processor speed.
It is, therefore, desirable to have an interrupt delivery mechanism that operates at a high clock rate to match the speed of new host processors and at the same time provides an efficient means to transfer message to the host processor.